Usage of an SDRAM as storage for correction and track buffering in frontend ICs of optical recording or reproduction devices

ABSTRACT

A method and arrangement for using Synchronous Dynamic Random Access Memory (SDRAM) as storage for correction and track buffering in front end ICs of optical recording or reproduction devices. Data to be stored or read is organized in appropriate bursts for accelerating the SDRAM (SDR) traffic. The SDRAM is built around two banks of memory, and are accessed using a pipelined address logic, thereby accelerating access speeds.

This application claims the benefit under 35 U.S.C. §365 ofInternational Application PCT/EP00/12551, filed Dec. 12, 2000, whichclaims the benefit of European Application No. 99125206.5, filed Dec.17, 1999.

FIELD OF THE INVENTION

The present invention relates to a method and an arrangement for theusage of an SDRAM as storage for correction and track buffering infrontend ICs of optical recording or reproduction devices, and moreparticularly to a method and an arrangement for the usage of an SDRAM asstorage for correction and track buffering in DVD frontend ICs whichalso can be used for CD applications.

BACKGROUND OF THE INVENTION

A conventional optical recording or reproduction device comprises anSRAM or a DRAM storage for correction and track buffering in frontendICs of optical recording or reproduction devices.

The SDRAM is built around two banks of memory, which are accessed byparticular pipelined address logic. In contrast to the normal DRAMSaddressing can be done in parallel to the data operation and dependingon the mode chosen a burst of consecutive locations is operated. Thisaccelerates the speed compared to the common DRAM drastically, on theother hand needs some additional buffering and address control.

SDRAM is an acronym for Synchronous DRAM that means a DRAM technologythat uses a clock to synchronize signal input and output on a memorychip. The clock is generated in the driving IC and derived from it'ssystem clock so that the timing of the memory chips and the timing ofthe driving IC are in synchronization. The data streams for storing,correction and track buffering in frontend ICs of optical recording orreproduction devices are due to several different modes, asynchronousdata streams and are not designed in a way that it can be handleddirectly within an SDRAM because it has no defined burst structure aswell as a constant speed as it is commonly used in computerapplications. An adaptation of the streams for SDRAM usage is thereforenecessary.

A system decoder for high-speed data transmission with track buffer foran optical disc player has been disclosed by GB-A-2 321 334. Said systemdecoder includes a track buffer memory, a first FIFO memory forreceiving data descrambled and error-detected and outputting the data bya unit of plural words, a second FIFO memory for receiving data from thetrack buffer memory and outputting the data by the unit of plural words,and a track buffer controller writing data in the first FIFO memory intothe track buffer memory in a page mode, and reading the data written inthe track buffer memory in a page mode to output the read data to thesecond FIFO memory. The track buffer memory includes a data area intowhich main data is written, an error information area into which errorinformation for the main data is written and a microcomputer area intowhich a microcomputer of the optical disc reproduction apparatus writesdata.

SUMMARY OF THE INVENTION

It is an object of the invention to create a method and an arrangement,which make it possible to use an SDRAM as storage for correction andtrack buffering in frontend ICs of optical recording or reproductiondevices.

A frontend IC of an optical recording or reproduction device is designedto reconstruct the data from an optical disc and perform the errorchecks; in some embodiments a correction of the found errors and astorage of the data to compensate physical fluctuations of the readingunit are foreseen; this facility is called track buffer mode.

In accordance with an aspect of the invention the data to be stored orread are organized in appropriate bursts for accelerating the SDRAMtraffic.

The SDRAM is built around two banks of memory, which are accessed by aparticular pipelined address logic, and accelerates the speed comparedto the common DRAM drastically. Most benefit of these features areachieved if the data transfer is done burstwise and if it is organizedin the memory so that the access can be done in a so-called ping-pongmode, i.e. changing the bank at each access.

If the frontend IC is chosen with an external SDRAM an interface has tosupervise the data transfer to and from that external SDRAM and toorganize the external SDRAM. Therefore depending on the functional modethe tasks change:

-   A) The following four tasks must be handled in the track buffer    mode:

A system decoder for high-speed data transmission with track buffer foran optical disc player has been disclosed by GB-A-2 321 334. Said systemdecoder includes a track buffer memory, a first FIFO memory forreceiving data descrambled and error-detected and outputting the data bya unit of plural words, a second FIFO memory for receiving data from thetrack buffer memory and outputting the data by the unit of plural words,and a track buffer controller writing data in the first FIFO memory intothe track buffer memory in a page mode, and reading the data written inthe track buffer memory in a page mode to output the read data to thesecond FIFO memory. The track buffer memory includes a data area intowhich main data is written, an error information area into which errorinformation for the main data is written and a microcomputer area intowhich a microcomputer of the optical disc reproduction apparatus writesdata.

-   A1) Store the raw data coming from the Reed Solomon into the    external SDRAM by help of the synchronization signals. While the    REED-SOLOMON block performs the further following inner/outer    corrections after the data was delivered by the REED-SOLOMON buffer    the data of another ECC block is sent from the REED-SOLOMON buffer    interface. Therefore the area must be as large as two ECC-blocks.-   A2) When the Reed Solomon sends the data for correcting, the    correction of the stored raw data has to be performed. Depending on    how and when the Reed Solomon makes this data available the external    SDRAM interface has to access randomly symbols from the ECC-block,    to update it due to the correction data and to store it back.-   A3) When the correction task of an ECC block is finished a track    buffer control unit is informed and starts reading burst wise the    corrected data. The symbols must be descrambled bitwise and the    so-called EDC-check must be performed that concerns a final    redunancy check for sectors of the datastream; after a fixed latency    the descrambled data are written back via the external SDRAM address    unit to the so called track buffer area in the SDRAM. This area is    divided into sectors whose content that means the position and    validity is controlled by the track buffer control unit.-   A4) On request of the backend interface or the internal    microcontroller the track buffer control unit requests sectors to    read them from the track buffer area to the output buffer. To adapt    the SDRAM speed to the speed of the backend a handshake procedure    between the backend interface and the external SDRAM interface is    foreseen. The control, which data are to be sent, is made by the    track buffer control unit.-   B) In a ramless REED-SOLOMON configuration the memory control can be    used as a buffer for the raw data and the offset mask sent by the    REED-SOLOMON before the backend interface can fetch them in an    appropriate manner.-   C) In the so called backward compatible configuration the SDRAM    interface has to perform the tasks A1 and A2 before it sends the    data to the part of the front end IC which performs the bitwise    descrambling and EDC calculation according to the first part of task    A3. The corrected and descrambled data are then sent back to the    memory control which makes-them available for the backend interface    adding the EDC-result at the end of each sector.

In case of the CD-modes the task A1 stores the incoming bitstream in thememory formed by said SDRAM. As the correction is done in the ReedSolomon block task A2 is not needed. The tasks A3 and A4 are performedas it is done in the DVD-mode where the trackbuffer control unitmodifies the data according to the CD-necessities.

To perform all tasks the memory and timing control has to keep thebuffers for adapting the different speeds of incoming and outgoing datastreams and the control of the internal bus which in a REED-SOLOMONconfiguration using a RAM is connected to the SDRAM interface containingthe address counters for the different tasks. In ramless REED-SOLOMONconfiguration the memory and timing control can organize in time andorder the outgoing data streams to facilitate the task of the backendinterface.

In the following sections the mode A is assumed; for the otherconfigurations the data transfer is bypassed the obsolete blocks.

The arrangement according to the invention has the following blocks:

Reed Solomon Block

This block has to strip off the parity data from the data stream comingpreferable from a buffer and sends it to the SDRAM address unit. Afterthe correction data is calculated the update byte and the location ofthe correction must be sent to the SDRAM address unit, which has toperform the correction and store back the corrected symbol.

Track Buffer Control Unit

When the ECC-correction is performed the ECC block is must be moved fromthe so called ECC buffer area of the SDRAM to the so called track bufferarea. The track buffer control unit gets a ready signal and asector-wise read of the corrected data from the ECC buffer is started,the bits were descrambled, the ESD of the current sector calculated andthe result stored back to the TR buffer area of the SDRAM following thesymbolic location controlled by the track buffer control unit.

When the sector is finished the track buffer control unit decides if thecurrent sector is valid and increments the location for the next sectoror keeps it.

For the backend IC the track buffer control unit handles requests forsending sectors to it verifying that the requested sectors are containedin the trackbuffer area. If they are the request is forwarded to theSDRAM address unit, initializing the backend stream by sending therequested sector address. The backend interface informs the track buffercontrol unit of the end of the currently received sector.

In the ramless REED-SOLOMON functional configuration the raw data can besent via the same lines while the correction mask, which is performed byoffset and address, may be put to an additional line with a controlsignal to the backend interface when this data is available. Thecoordination and format of the stream of data and correction mask is anautonomous task of the backend interface unit.

SDRAM Address Unit

This unit has to answer for the requests previously described and has tomake the bookkeeping of the memory resources. Depending on the SDRAMsize and its timing specifications a proper mapping of the data to thephysical SDRAM address must be made.

The SDRAM is functionally divided into two areas:

-   -   The ECC-block area and the    -   Track buffer area.

The ECC-block area must contain at least two ECC blocks because thecalculation of the error correction can only be started after theECC-block is completely read in from the REED SOLOMON part. The numberof inner/outer-runs performed by the Reed Solomon unit determines thetime when the correction data are available and can be sent to the-SDRAMaddress unit. If these processes are finished before the alternateECC-block is read in only two ECC-blocks need to be stored in the SDRAM;otherwise the number must be increased.

The rest of the SDRAM can be filled by the track buffer area, which isorganized in sectors. The track buffer control unit keeps across-reference between a long sector ID and the location in the trackbuffer area.

To accelerate the data exchange SDRAMs pipeline the addressing and thedata traffic:

While the data are received or sent burst wise with a preset length theaddress for the start of the next burst package can be sent to the SDRAMdepending on address and direction of the currently transferred data.

The incrementation of the address during burst operation is doneinternally by the SDRAM.

The addressing of SDRAMs is explained in more detail below what willclarify the need for this decoupling.

The usage of the SDRAM speeds up the SDRAM traffic of the DVD frontendIC allowing more sophisticated features in handling the data flow in theIC; the organization of the dataflow is easier to because bandwidthrestrictions are avoided.

BRIEF DESCRIPTION OF THE DRAWINGS

The invention will now be described with reference to the accompanyingdrawings, in which:

FIG. 1 is a block diagram for the usage of an SDRAM as storage forcorrection and track buffering in frontend ICs of optical recording orreproduction devices,

FIG. 2 is a schematic of the structure of a SDRAM,

FIG. 3 is a schematic of a possible write sequence of the SDRAM and

FIG. 4 is a schematic of a possible read sequence of the SDRAM.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates the arrangement of an SDRAM SDR as storage forcorrection and track buffering in frontend ICs of optical recording orreproduction devices as for example a DVD-player. Blocks and connectionsas well as control lines for CD-modes are not included.

The DVD-player using an SDRAM SDR as storage for correction and trackbuffering in the frontend IC comprises according to FIG. 1 a ReedSolomon Decoder RSD, a memory controller MC, a track buffer controllerTBC, a backend interface BEI and said SDRAM SDR. Reed Solomon DecoderRSD, memory controller MC and said SDRAM SDR are connected to a systemclock CLK. The Reed Solomon Decoder RSD receives preprocessed dataDATA_IN provided from an optical recording medium as for example a DVD.The preprocessed data DATA_IN are incoming symbols to the Reed SolomonDecoder RSD as well as not shown ECC-, sector- and frame-start signalsfrom a not shown acquisition part. For the reason of simplification onlysummarized connections between the unites are shown in FIG. 1 which aremostly formed by several lines. The Reed Solomon Decoder RSD isconnected with said memory controller MC to store and exchangecorrection data RS_DATA with memory controller MC and provides via afurther connection corrected data CR_DATA for said memory controller MCand a track buffer controller TBC which provides via connections trackinformation to_TR and track addresses tr_addr for the memory controllerMC. Memory controller MC and SDRAM SDR are connected to exchange datavia a bus DBUS controlled by addresses addr and RAM control signalsram_ctrl. And the mentioned backend interface BEI receives requesteddata to_BE from memory controller MC, which have been requested byrequest commands req, sent to the track buffer controller TBC.

The units shown in FIG. 1 are described in more detail below.

Reed Solomon Decoder RSD

This block strips off the parity data from incoming preprocessed dataDATA_IN and sends it via a memory controller MC to the SDRAM SDR. Afterthe correction data is calculated the faulty data on the SDRAM SDR isexchanged by the corrected data.

1.1 The track Buffer Controller TBC:

When the ECC-correction is performed the ECC block stored in the ECCarea of the SDRAM SDR is ready for a transfer to the track buffer area.The track buffer controller TBC reads sector-wise the corrected datafrom the ECC area, prepares the validity decision and coordinates thestorage of them via a memory control in the track buffer area of theSDRAM SDR.

On request of the track buffer controller TBC the memory controller MCfetches the data sectorwise from the track buffer area of the SDRAM SDRand delivers them to the backend interface BEI.

1.2 Memory Controller MC

This unit has to answer the requests previously described and makes thebookkeeping of the memory resources. Depending on the size of SDRAM SDRand its timing specifications a proper mapping of the data to thephysical address is made.

The SDRAM SDR is functionally divided into two areas:

-   -   The ECC-block area and the    -   Track buffer area.

The ECC-block area must contain at least two ECC blocks because thecalculation of the error correction can only be started after theECC-block is completely read in from the Reed Solomon Decoder RSD. Thenumber of inner/outer-runs performed by the Reed Solomon Decoder RSDdetermines the time when the corrected data CR_DATA is available and canbe sent to the memory controller MC. If these processes are finishedbefore the alternate ECC-block is read in only two ECC-blocks need to bestored in the SDRAM SDR; otherwise the number must be increased.

The track buffer area of the SDRAM SDR, which is organized in sectors,can fill the rest of the SDRAM SDR.

The memory controller MC has to keep the physical addresses of therelated processes respecting the size and timing specification of theused SDRAM SDR. The data are sent burst wise with a preset burst lengthto SDRAM SDR and the address for the start of the next burst package issent to the SDRAM SDR to accelerate the data exchange in the pipeline,the addressing and the data traffic. The SDRAM SDR does theincrementation of the address during burst operation internally.

The SDRAM SDR as shown in FIG. 2 is built around two banks Bank 0 andBank1 of memory, which are accessed by particularly pipelined addressand RAM control signals ram_ctrl. In contrast to normal DRAMS addressingcan be widely done in parallel to the data operation which depends onthe locations of the consecutive bursts. This accelerates the speedcompared to the common DRAM drastically.

Most benefit of these features is achieved if the data transfer is doneburstwise and if it is organized in the memory so hat the access can bedone in ping-pong mode, i.e. changing the bank at each access.

The system clock CLK synchronizes all transfers although severaldifferent data speeds have to be handled.

1.2.1 Operation of SDRAM SDR:

As an example two FIGS. 3 and 4 show the so called ping-pong operationas used for a SDRAM SDR with 16 Mbit Memory setting the so-calledCAS-latency to a number of 2 for the used system clock CLK. Theinput-output operations of SDRAM SDR are performed as shown in FIGS. 3and 4.

Each of the FIGS. 3 and 4 show a first row a illustrating the operationsperformed on bank Bank 0 and Bank1 of the memory of SDRAM SDR. Eachtransfer starts by activating the bank denoted by ram_ctrl followed bythe read or write command performed by setting the ram_ctrl-signals ofFIG. 1. The result of the operation is shown as DIN or DOUT denoting thedirection of the data.

A second row b illustrates system clock CLK, a third row c showsspecific addresses addr which are controlled by memory controller MC.They are split into row-address R0,R1 . . . and column-address Ca, Cb, .. . sent at the appropriate time.

A fourth row d illustrates data, which correspondingly occur on busDBUS. The items are marked with the related locations R. and C. as senton the address signals addr and an incremented number of the location inthe burst.

The output operation as shown in FIG. 3 demonstrate successive readrequests on mutual banks which have addresses and data active at thesame time whereas FIG. 4 demonstrates the same for write operation.

The usage is not limited to the specific SDRAM as mentioned in theembodiment and a person skilled in the art can easily modify it withoutto leave the invention.

1. An optical recording or reproduction apparatus having a track bufferand a track buffer controller for high-speed data transmissioncharacterised in that—a Synchronous Dynamic Random Access Memory (SDRAM)is coupled to a memory controller (MC) which is furthermore connectedwith a Reed Solomon Decoder (RSD) and the track buffer controller (TBC)to form a front end IC of said optical recording or reproduction deviceand is used as storage for correction and track buffering and data to bestored in said Synchronous Dynamic Random Access Memory (SDRAM) or to beread out from said Synchronous Dynamic Random Access Memory (SDRAM) isorganized in bursts by the memory controller (MC) for accelerating thetraffic of the Synchronous Dynamic Random Access Memory (SDRAM). 2.Apparatus according to claim 1 characterised in that the SynchronousDynamic Random Access Memory (SDRAM) is coupled to a memory controller(MC) which forms an interface to supervise a data transfer to and fromthe Synchronous Dynamic Random Access Memory (SDRAM) and to organize theSynchronous Dynamic Random Access Memory (SDRAM) burstwise.
 3. Apparatusaccording to claim 1 characterised in that the Synchronous DynamicRandom Access Memory (SDRAM) accesses randomly symbols from an ECC(Error Correction Code)-block to update it due to correction data(RS_DATA) and to store it back as corrected data (CR_DATA) in a trackbuffer area of the Synchronous Dynamic Random Access Memory (SDRAM). 4.Apparatus according to claim 1 characterised in that said from end ICperforms bitwise descrambling and Error Detection Code (EDC) calculationof data.
 5. An optical recording or reproduction apparatus having atrack buffer and a track buffer controller for high-speed datatransmission characterised in that a Synchronous Dynamic Random AccessMemory (SDRAM) is provided, which is used as storage for correction andtrack buffering and data to be stored in said Synchronous Dynamic RandomAccess Memory (SDRAM) or to be read out from said Synchronous DynamicRandom Access Memory (SDRAM) is organized in bursts by a memorycontroller (MC) for accelerating the traffic of the Synchronous DynamicRandom Access Memory (SDRAM), which stores raw data coming from a ReedSolomon Decoder (RSD) into the Synchronous Dynamic Random Access Memory(SDRAM) by help of system clock CLK while the Reed Solomon Decoder (RSD)performs a second and further following inner/outer correction after thedata was delivered by the Reed Solomon Decoder (RSD) and that dependingon how and when the Reed Solomon Decoder (RSD) makes this data availablethe Synchronous Dynamic Random Access Memory (SDRAM) accesses randomsymbols from the ECC-block to update it due to the correction data (RSDATA) and to store it back as corrected data (CR_DATA) in a track bufferarea of the Synchronous Dynamic Random Access Memory (SDRAM). 6.Apparatus according to claim 5 characterised in that the SynchronousDynamic Random Access Memory (SDRAM) in a case of a CD reproduced by theoptical recording or reproduction apparatus raw data coming from a ReedSolomon Decoder (RSD) are stored into the Synchronous Dynamic RandomAccess Memory (SDRAM) by help of a system clock (CLK) and are stored toSynchronous Dynamic Random Access Memory (SDRAM) under supervision of atrack buffer controller (TBC) according to the CD necessities. 7.Apparatus according to claim 6 characterised in that raw data are storedfrom the Reed Solomon Decoder (RSD) via memory controller (MC) toperform the correction.
 8. Apparatus according to claim 5 characterisedin that the Synchronous Dynamic Random Access Memory (SDRAM) is used ina case of a DVD reproduced by the optical recording or reproductionapparatus raw data coming from a Reed Solomon Decoder (RSD) are storedinto the Synchronous Dynamic Random Access Memory (SDRAM) by help of asystem clock (CLK) while the Reed Solomon Decoder (RSD) performsinner/outer corrections in the Synchronous Dynamic Random Access Memory(SDRAM) after the data was delivered by the Reed Solomon Decoder (RSD),and the corrected data are modified and restored under supervision of atrack buffer controller (TBC) according to the DVD necessities.